®
R&S
FPL1000
A separate LMARgin register exists for each active channel and for each window.
It can be read using the commands
STATus:QUEStionable:LMARgin:CONDition? and
STATus:QUEStionable:LMARgin[:EVENt]?.
Table 9-11: Meaning of the bits used in the STATus:QUEStionable:LMARgin register
Bit No.
0
1
2
3
4
5
6
7
8 to 14
15
9.2.2.12
STATus:QUEStionable:POWer register
The STATus:QUEStionable:POWer register contains information about possible
overload situations that may occur during operation of the R&S FPL1000. A separate
power register exists for each active channel.
You can read out the register with
STATus:QUEStionable:POWer[:EVENt]?
Table 9-12: Meaning of the bits used in the STATus:QUEStionable:POWer register
Bit No.
0
1
2
Manuel d'utilisation 1179.5860.09 - 12
Meaning
LMARgin 1 FAIL
This bit is set if limit margin 1 is violated.
LMARgin 2 FAIL
This bit is set if limit margin 2 is violated.
LMARgin 3 FAIL
This bit is set if limit margin 3 is violated.
LMARgin 4 FAIL
This bit is set if limit margin 4 is violated.
LMARgin 5 FAIL
This bit is set if limit margin 5 is violated.
LMARgin 6 FAIL
This bit is set if limit margin 6 is violated.
LMARgin 7 FAIL
This bit is set if limit margin 7 is violated.
LMARgin 8 FAIL
This bit is set if limit margin 8 is violated.
Not used
This bit is always 0.
Meaning
OVERload
This bit is set if an overload occurs at the RF input, causing signal distortion but not yet causing
damage to the device.
The R&S FPL1000 displays the keyword "RF OVLD".
Unused
Unused
Network operation and remote control
STATus:QUEStionable:POWer:CONDition?
Status reporting system
or
573
573