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R&S
FPL1000
Table 9-6: Meaning of the bits used in the STATus:QUEStionable:ACPLimit register
Bit No.
0
1
2
3
4
5
6
7
8-14
15
9.2.2.7
STATus:QUEStionable:EXTended register
The STATus:QUEStionable:EXTended register contains further status information
not covered by the other status registers of the R&S FPL1000. A separate EXTended
register exists for each active channel.
You can read out the register with
STATus:QUEStionable:EXTended[:EVENt]?
or
Table 9-7: Meaning of the bits used in the STATus:QUEStionable:EXTended register
Bit No.
0
1
2 to 14
15
Manuel d'utilisation 1179.5860.09 - 12
Meaning
ADJ UPPer FAIL
This bit is set if the limit is exceeded in the upper adjacent channel
ADJ LOWer FAIL
This bit is set if the limit is exceeded in the lower adjacent channel.
ALT1 UPPer FAIL
This bit is set if the limit is exceeded in the upper 1st alternate channel.
ALT1 LOWer FAIL
This bit is set if the limit is exceeded in the lower 1st alternate channel.
ALT2 UPPer FAIL
This bit is set if the limit is exceeded in the upper 2nd alternate channel.
ALT2 LOWer FAIL
This bit is set if the limit is exceeded in the lower 2nd alternate channel.
ALT3 ... 11 LOWer/UPPer FAIL
This bit is set if the limit is exceeded in one of the lower or upper alternate channels 3 ... 11.
CACLR FAIL
This bit is set if the CACLR limit is exceeded in one of the gap channels.
Unused
This bit is always 0.
Meaning
not used
INFO
This bit is set if a status message is available for the application.
Which type of message occurred is indicated in the
ister.
Unused
This bit is always 0.
Network operation and remote control
STATus:QUEStionable:EXTended:CONDition?
STATus:QUEStionable:EXTended:INFO reg-
Status reporting system
570
570
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