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R&S
FPL1000
& logic AND
of all bits
logic OR
*) one register for
each channel
SRQ
&
RQS/MSS
&
ESB
&
MAV
&
&
SRE
STB
&
&
&
&
&
&
PPE
ISTflag
Error/ Event Output
Queue
Buffer
ESE
Figure 9-1: Graphical overview of the R&S FPL1000 status registers hierarchy
All status registers have the same internal structure.
9.2.2
Contents of the status registers
In the following sections, the contents of the status registers are described in more
detail.
Manuel d'utilisation – 1179.5860.09 - 12
not used
15
15
14
14
13
13
12
12
11
11
10
10
9
8
7
HCOPy in progress
6
5
4
Waiting for TRIGger
3
MEASuring
2
SWEeping
1
0
S
CALibrating
TATus:OPERation
STAT:QUES:ACPLimit *)
15
14
not used
13
12
11
ACPLimit
10
SYNC
LMARGin
LIMit
CALibration (=UNCAL)
FREQuency
TEMPerature
POWer
TIME
Battery LOW
EXTended
STATus:QUEStionable
15
...
5
4
&
Power On
3
&
User Request
2
&
Command Error
1
Sweep time too low
&
Execution Error
0
Device Dependent
&
Error
STAT:QUES:TIME *)
Query Error
&
&
Operation Complete
ESR
Network operation and remote control
not used
15
14
13
12
11
10
CACLR FAIL
LMARgin 8 FAIL
ALT3...11 LOWer/UPPer FAIL
LMARgin 7 FAIL
ALT2 LOWer FAIL
LMARgin 6 FAIL
ALT2 UPPer FAIL
LMARgin 5 FAIL
ALT1 LOWer FAIL
LMARgin 4 FAIL
ALT1 UPPer FAIL
LMARgin 3 FAIL
ADJ LOWer FAIL
LMARgin 2 FAIL
LMARgin 1 FAIL
ADJ UPPer FAIL
STAT:QUES:LMARgin<n> *)
15
...
not used
15
...
External REFerence
LO UNLocked
OVEN COLD
STAT:QUES:TEMPerature *)
STAT:QUES:FREQuency *)
15
not used
not used
...
5
4
3
2
INFO
1
0
STAT:QUES:EXTended *)
Status reporting system
not used
not used
15
14
13
12
11
10
9
8
LIMit 8 FAIL
7
LIMit 7 FAIL
6
5
LIMit 6 FAIL
4
LIMit 5 FAIL
LIMit 4 FAIL
3
LIMit 3 FAIL
2
LIMit 2 FAIL
1
LIMit 1 FAIL
0
S
TAT:QUES:LIMit<n> *)
15
not used
not used
...
9
8
7
6
5
4
INPut_overload
3
IF_OVerload
2
UNDerload
1
OVERload
0
Frontend temp. error
STAT:QUES:POWer *)
15
not used
...
5
4
FATal
3
ERRor
2
WARNing
1
INFO
0
MESSage
STAT:QUES:EXTended:INFO *)
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