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Appendix
FD-05 is set as 1:
ADR
CMD
Byte No.
Data F002H high-order
Data F002H low-order
Data F003H high-order
Data F003H low-order
CRC CHK low-order
CRC CHK high-order
CMD code: 06H, write one word. For example: write 5000 (1388H) in F00AH address of
frequency convertor with slave address being 02H.
CMD message of host
ADR
CMD
Data address high-order
Data address low-order
Data content high-order
Data content low-order
CRC CHK low-order
CRC CHK high-order
Response message of slave
ADR
CMD
Data address high-order
Data address low-order
Data content high-order
Data content low-order
CRC CHK low-order
CRC CHK high-order
Verification mode-CRC verification mode: CRC (Cyclical Redundancy Check) uses RTU frame
format, and message includes error detection domain based on CRC method. CRC domain detects the
contents of whole message. CRC domain is two-byte and includes 16-bit binary system value. It's added
to message after calculation by transmission equipment. Receiving equipment recalculates CRC of
received message and compares with value in received CRC domain. If two CRC values are not equal,
the transmission is wrong.
CRC firstly stores 0xFFFF, and then calls a course to process successive 8-bit bytes in message
and value in current register. Only 8Bit data in each character is valid for CRC, start bit, stop bit and
parity check bit are invalid.
Specification of high-performance vector convertor
01H
03H
04H
00H
00H
00H
01H
CRC CHK value to be calculated
02H
06H
F0H
0AH
13H
88H
CRC CHK value to be calculated
02H
06H
F0H
0AH
13H
88H
CRC CHK value to be calculated
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