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STATus:OPERation:CONDition?
Returns the sum of the bits in the condition register for the
register is read-only; bits are not cleared when read.
A condition register continuously monitors the state of the instrument. Condition register bits are updated
in real time; they are neither latched nor buffered.
Parameter
Typical Return
(none)
+32
Read the condition register (bit 5 is set):
STAT:OPER:COND?
The condition register bits reflect the current condition. If a condition goes away, the corresponding
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bit is cleared in the condition register.
STATus:OPERation:ENABle <enable_value>
STATus:OPERation:ENABle?
Enables bits in the enable register for the
reported to the Status Byte. An enable register defines which bits in the event register will be reported to
the Status Byte register group. You can write to or read from an enable register.
A decimal value that corresponds to the binary-weighted sum of the bits in the
register.
Enable bit 5 (decimal value 32) in the enable register:
STAT:OPER:ENAB 32
Use the <enable> parameter to specify which bits will be reported to the Status Byte. The decimal
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value specified corresponds to the binary-weighted sum of the bits you wish to enable in the register.
For example, to enable bit 5 (decimal value = 32) and bit 9 (decimal value = 512), the corresponding
decimal value would be 544 (32 + 512).
A
STATus:PRESet
clears all bits in the enable register.
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The <enable> setting is nonvolatile; it does not change after a Factory Reset (*RST) , Instrument Pre-
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set (SYSTem:PRESet), Status Preset (STATus:PRESet) or Clear Status (*CLS).
The
*PSC
command controls whether the enable register is cleared at power on.
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Keysight Truevolt Series Operating and Service Guide
Standard Operation Register
Parameter
SCPI Programming Reference
Standard Operation Register
group. The selected bits are then
+32
group. This
Typical Return
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