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4 Using the Regenerative Power System
adjusting the filter frequency also depends on the compensation setting and the load impedance. The
filter frequency setting does not affect the unit's transient response to a load change.
The following table summarizes the effect that the compensation settings have on the CV
Programming Speed Characteristics for all models.
Setting
0 Fast
no load, 0.1%-100% of rating
1 Medium
no load, 0.1%-100% of rating
2 Slow
no load, 0.1%-100% of rating
The following table describes the CV small signal bandwidth characteristics for all models
CV programming small signal bandwidth (-3dB) at no load
Setting
0 Fast
1 Medium
2 Slow
Front Panel Menu Reference
Select Output\Advanced\Bandwidth\Voltage.
Select either 0, 1, or 2. If desired, enter the pole frequency in the
Frequency field. Then press Select.
Current compensation
The current compensation provided is suited to handle a wide, range of total lead and DUT inductance
with a relatively fast programming response (see
impact of load lead inductance, paralleling additional sets of load leads to lower the net inductance
can help, especially if load lead lengths are long.
<frequency> - specifies the low-pass corner frequency of a filter applied to the programming signal.
Refer to the previous description under Voltage Compensation modes for a description of use case
tradeoffs of changing the <frequency> setting.
The following table summarizes the effect that the compensation settings have on the CC
Programming Speed Characteristics for all models.
Step Conditions
AC short at >10% Vrating,
0.1%-100% of rating
The CC programming small signal bandwidth characteristic at -3dB is 3.5 kHz for all models.
110
Step Conditions
Frequency
100 kHz
100 kHz
100 kHz
Frequency
2.5 kHz
1 kHz
350 Hz
Frequency
Rise/fall time
10%-90% of step
100 kHz
100 µs
Keysight RP7970 & RP7980 Series Operating and Service Guide
Rise/fall time
10%-90% of step
0.2 ms
0.5 ms
33 ms
SCPI Command
To set the voltage compensation bandwidth:
VOLT:BWID:RANG 0 | 1 | 2
To specify the pole frequency:
VOLT:BWID:LEV 0 | 1 | 2, <frequency>
Inductance Load Boundary
Settling time
to 0.1% of step
200 µs
Settling time
to 0.1% of step
1 ms
2.5 ms
110 ms
graph). To reduce the
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