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Status Byte Register
This register summarizes the information from all other status groups as defined in the IEEE 488.2
Standard Digital Interface for Programmable Instrumentation. Refer to
The following table describes the Status Byte register bit assignments.
Bit
Bit Name
0
not used
1
not used
2
Error Queue
3
Questionable Status Summary
4
Message Available
5
Event Status Summary
6
Master Status Summary
7
Operation Status Summary
Master Status Summary and Request for Service Bits
MSS is a real-time (unlatched) summary of all Status Byte register bits that are enabled by the Service
Request Enable register. MSS is set whenever the instrument has one or more reasons for requesting
service. *STB? reads the MSS in bit position 6 of the response but does not clear any of the bits in the
Status Byte register.
The RQS bit is a latched version of the MSS bit. Whenever the instrument requests service, it sets the
SRQ interrupt line true and latches RQS into bit 6 of the Status Byte register. When the controller does
a serial poll, RQS is cleared inside the register and returned in bit position 6 of the response. The
remaining bits of the Status Byte register are not disturbed.
Error and Output Queues
The Error Queue is a first-in, first-out (FIFO) data register that stores numerical and textual description
of an error or event. Error messages are stored until they are read with
overflows, the last error/event in the queue is replaced with error -350,"Queue overflow".
The Output Queue is a first-in, first-out (FIFO) data register that stores messages until the controller
reads them. Whenever the queue holds messages, it sets the MAV bit (4) of the Status Byte register.
Keysight RP7900 Series Operating and Service Guide
Decimal
Value
not used
0 is returned
not used
0 is returned
4
One or more errors in the Error Queue. Use SYSTem:ERRor? to
read and delete errors.
8
One or more bits are set in the Questionable Data Register. Bits
must be enabled, see STATus:QUEStionable:ENABle.
16
Data is available in the instrument's output buffer.
32
One or more bits are set in the Standard Event Register. Bits must
be enabled, see *ESE.
64
One or more bits are set in the Status Byte Register and may gen-
erate a Request for Service. Bits must be enabled, see *SRE.
128
One or more bits are set in the Operation Status Register. Bits
must be enabled, see STATus:OPERation:ENABle.
5 SCPI Programming Reference
Status
Diagram.
Definition
SYSTem:ERRor?
If the queue
255
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