Metrix GX1010 Notice De Fonctionnement page 130

2
3
Bit 1 -
Bit 0 -
5.1.5.2. Status Byte Register and Service Request Enable Register
These two registers are implemented as required by the IEEE std. 488.2.
Any bits set in the Status Byte Register which correspond to bits set in the Service Request
Enable Register will cause the RQS/MSS bit to be set in the Status Byte Register, thus
generating a Service Request on the bus.
The Status Byte Register is read either by the ∗STB? command, which will return MSS in
bit 6, or by a Serial Poll which will return RQS in bit 6. The Service Request Enable register
is set by the ∗SRE <nrf> command and read by the ∗SRE? command.
Bit 7 -
Bit 6 -
Bit 5 -
Bit 4 -
Bit 3 -
Bit 2 -
Bit 1 -
Bit 0 -
GX1010
Deadlock error
Unterminated error
Not used.
Operation Complete. Set in response to the ∗OPC command.
Not used.
RQS/MSS. This bit, as defined by IEEE Std. 488.2, contains
both the Requesting Service message and the Master Status
Summary message. RQS is returned in response to a Serial
Poll and MSS is returned in response to the ∗STB? command.
ESB. The Event Status Bit. This bit is set if any bits set in the
Standard Event Status Register correspond to bits set in the
Standard Event Status Enable Register.
MAV. The Message Available Bit. This will be set when the
instrument has a response message formatted and ready to
send to the controller. The bit will be cleared after the Response
Message Terminator has been sent.
Not used.
Not used.
Not used.
Not used.
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