Sun Microsystems Sun Fire X4100 Guide De Configuration Et De Maintenance page 51

2.4.4.31 Ecran SouthBridge Configuration du menu Chipset du BIOS
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* South Bridge Chipset Configuration
* *************************************************** * SMBUS 2.0 Controller
* 2.0 SM Bus Controller
* Restore on AC/Power Loss
* Power Button Behavior
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* HT Link 0 P-Comp Mode
* HT Link 0 N-Comp Mode
* HT Link 0 RZ-Comp Mode
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2.4.4.32 Ecran PCI-X Configuration du menu Chipset du BIOS
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* PCI-X Chipset Configuration
* *************************************************** * enabled for 8131
* Errata 56 PCLK
* HT Link 0 P-Comp Mode
* HT Link 0 N-Comp Mode
* HT Link 0 RZ-Comp Mode
* HT Link 1 P-Comp Mode
* HT Link 1 N-Comp Mode
* HT Link 1 RZ-Comp Mode
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Chipset
* Enable/disable
[Enabled] * in South Bridge
[Power Off] *
[Instant Off] *
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[Auto] *
[Auto] *
[Auto] *
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* **
* **
* +-
* F1
* F10
* ESC
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Chipset
* PCI clock is disabled/ *
[Enabled] * Errata 56 if a PCI
[Auto] * card behind 8131
[Auto] * bridge has more than
[Auto] * 4 functions and bus
[Auto] * speed is 133 MHz.
[Auto] *
[Auto] *
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* **
* **
* +-
* F1
* F10
* ESC
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Chapitre 2 Mise sous tension et définition des paramètres du BIOS
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Select Screen *
Select Item *
Change Option *
General Help *
Save and Exit *
Exit *
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Select Screen *
Select Item *
Change Option *
General Help *
Save and Exit *
Exit *
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