Ssi Interface; Principle - Balluff BTL7-S5 Série Notice D'utilisation

BTL7-S5 _ _ D-M _ _ _ _ -T _ 2/3-S32/KA _ _ /FA _ _
Magnetostrictive Linear Position Sensor – Rod Style
6

SSI interface

6.1

Principle

SSI stands for Synchronous Serial Interface and describes
a digital synchronous interface with a differential clock line
and a differential data line.
With the first falling clock edge, the data word to be output
is buffered in the BTL to ensure data consistency. Data
output takes place with the first rising clock edge, i.e. the
BTL supplies a bit to the data line for each rising clock
edge. In doing so, the line capacities and delays of drivers
t when querying the data bits must be taken into account
v
in the controller.
The max. clock frequency f
The t time, also called monoflop time, is started with the
m
last falling edge and is output as the low level with the last
rising edge. The data line remains at low until the t
has elapsed. Afterwards, the BTL is ready again to receive
the next clock package.
SSIn
T
Clk
Clk
1
Data
MSB
T
Clk
Clk
t
Data
Clk
Data
T = 1 / f SSI clock period, SSI clock frequency
Clk Clk
T = 1 / f Sampling period, sampling rate
A A
n Number of bits to be transmitted (requires n+1 clock impulses)
t = 2 × T Time until the SSI interface is ready again
m Clk
t = 150 ns Transmission delay times (measured with a 1 m cable)
v
14 english
depends on the cable length.
Clk
time
m
2 3 4 5
t
v v
T
A
Position data is determined and output in a timely manner
and synchronous to the external sampling period. For
synchronous operation the sampling period T
the range T ≤ T .
A, min A
t
m
n n+1
LSB
must lie in
A