Données techniques
Diagramme bloc
INA
A/D
GAIN
GATE
MUTE
HP/LP
INB
A/D
GAIN
GATE
MUTE
HP/LP
INC
A/D
GAIN
GATE
MUTE
HP/LP
IND
A/D
GAIN
GATE
MUTE
HP/LP
DSP 204, DSP 206, DSP 408
28
Controller
GEQ
PEQ
PHASE
DEL AY
LINK
GEQ
PEQ
PHASE
DEL AY
LINK
GEQ
PEQ
PHASE
DEL AY
LINK
GEQ
PEQ
PHASE
DEL AY
LINK
XO VER
PEQ
GAIN
MUTE
XO VER
PEQ
GAIN
MUTE
XO VER
PEQ
GAIN
MUTE
XO VER
PEQ
GAIN
MUTE
4*8
MATRIX
XO VER
PEQ
GAIN
MUTE
XO VER
PEQ
GAIN
MUTE
XO VER
PEQ
GAIN
MUTE
XO VER
PEQ
GAIN
MUTE
COMP
LIMIT
PHASE
DEL AY
LINK
COMP
LIMIT
PHASE
DEL AY
LINK
COMP
LIMIT
PHASE
DEL AY
LINK
COMP
LIMIT
PHASE
DEL AY
LINK
COMP
LIMIT
PHASE
DEL AY
LINK
COMP
LIMIT
PHASE
DEL AY
LINK
COMP
LIMIT
PHASE
DEL AY
LINK
COMP
LIMIT
PHASE
DEL AY
LINK
D/A
OUT1
D/A
OUT2
D/A
OUT3
D/A
OUT4
D/A
OUT5
D/A
OUT6
D/A
OUT7
D/A
OUT8