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Test Point
Net Name
TP446
SW_PES_CLK
TP445
SW_PES_7
TP444
SW_PES_6
TP443
SW_PES_5
TP442
SW_PES_4
TP441
SW_PES_3
TP440
SW_PES_2
TP439
SW_PES_1
TP438
SW_PES_0
TP318
CD2#_B
TP319
101S16#_
TP320
MDO2_B
TP321
D2_B
TP322
MDO1_B
TP323
D1_B
TP324
MDO0_B
TP325
D0_B
TP326
MOSTR0_B
TP327
A0_B
TP328
MOVAL_B
TP329
A1_B
TP330
REG#_B
TP331
A2_B
TP332
INPACK#_B
TP333
A3_B
TP334
WAIT#_B
TP335
A4_B
TP336
RESET_B
TP337
A5_B
TP338
MCLKO_B
TP339
A6_B
TP340
A7_B
TP341
MD16_B
TP342
A12_B
TP343
MD15_B
TP344
MCLK1
TP345
MD14_B
TP346
MIVAL_B
TP347
MD13_B
TP348
IREQ#_B
TP349
MD12_B
TP368
WE#_B
TP369
MD11_B
TP370
A14_B
TP371
MD10_B
TP380
A13_B
TP381
M1STRT_B
TP382
A8_B
TP383
IOWR#_B
TP384
A9_B
TP385
IORD#_B
TP386
A11_B
TP387
VS1#_B
TP389
OE#_B
TP390
CE2#_B
TP391
A10_B
TP392
MDO7_B
TP393
CE1#_B
TP394
MDO6_B
TP395
D7_B
TP396
MDO5_B
TP397
D8_B
TP398
MDO4_B
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Function
Switch present transport clock
Switch present transport 7
Switch present transport 6
Switch present transport 5
Switch present transport 4
Switch present transport 3
Switch present transport 2
Switch present transport 1
Switch present transport 0
Not Card detect CI 2
Not 8 or 16 bit data access
Transport stream data out Bit 2
CI 2 Data Bus Bit 2
Transport stream data out Bit 1
CI 2 Data Bus Bit 2
Transport stream data out Bit 0
CI 2 Data Bus Bit 0
Transport stream out Packet start
CI 2 Address Bus Bit 0
Transport stream out Packet valid
CI 2 Address Bus Bit 1
CI 2 Register select
CI 2 Address Bus Bit 2
CI 2 Acknowledge data transfer
CI 2 Address Bus Bit 3
CI 2 Extended data transfer
CI 2 Address Bus Bit 4
CI 2 reset module CPU
CI 2 Address Bus Bit 5
CI 2 Transport stream packet clock out
CI 2 Address Bus Bit 6
CI 2 Address Bus Bit 7
CI 2 transport stream data in Bit 6
CI 2 Address Bus Bit 12
CI 2 transport stream data in Bit 5
CI 2 transport stream packet clock in
CI 2 transport stream data in Bit 4
CI 2 transport stream packet valid in
CI 2 transport stream data in Bit 3
CI 2 Interupt request from module
CI 2 transport stream data in Bit 2
CI 2 module memory write enable
CI 2 transport stream data in Bit 1
CI 2 Address Bus Bit 14
CI 2 transport stream data in Bit 0
CI 2 Address Bus Bit 13
CI 2 transport stream packet start in
CI 2 Address Bus Bit 8
CI 2 Module write enable
CI 2 Address Bus Bit 9
CI 2 Module read enable
CI 2 Address Bus Bit 11
CI 2 Module voltage sense pin 1
CI 2 Module memory output enable
CI 2 Module enable 2
CI 2 Address Bus Bit 10
CI 2 transport stream data out Bit 7
CI 2 Module enable 1
CI 2 transport stream data out Bit 6
CI 2 Data Bus Bit 7
CI 2 transport stream data out Bit 5
CI 2 Data Bus Bit 8
CI 2 transport stream data out Bit 4
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