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AUDIO OUTPUT
The left, right, centre and surround signals are output from pins 29, 28 26 and 25 of the MSP3410D (I400) and are then applied to
an operational amplifier (IF03) at pins 5, 10, 12 and 3 respectively. This adds 3dB of gain.
The outputs from IF03 for the left and right (pins 7 and 8) are supplied to both the audio amplifier (I401) via the attenuation networks
R443 / R439 & R446 / R447 and the phono outputs via buffer transistors QF02 and QF01.
The centre and surround outputs from IF03 (pins 14 and 1) are only supplied to the phono outputs via buffer transistors QF22 and
QF21.
The left and right output stage consists of one TDA7297 (I401) which is a dual bridge amplifier which in this case is driven to give
12W per channel @ 10% thd. The power output is limited by the Vcc supply to pins 3 & 13.
The left and right signals are input to pins 4 & 6 and the outputs obtained from pins 1& 2 and 14 & 15.
Warning. Neither output for either channel is connected to the chassis ground so caution must be taken if an oscilloscope and
other mains operated equipment with a common earth is to be used simultaneously when checking the audio outputs.
The TDA7297 has two control lines on pins 6 & 7. These control inputs are high when the outputs are active and low when muted.
The outputs from pins 2 and 14 of I401 are connected directly to pins 2 and 3 of P400. The outputs from pins 1 and 15 are
connected to pins 1 and 4 of P400 via the headphone socket J400. When a set of headphones is inserted the connections between
I401 and P400 are broken. The left and right outputs from pins 1 and 15 of I401are connected to ground via C438 / R438 & the left
headphone coil and C437 / R437 & the right headphone coil respectively. This method was used to limit the power dissipated in the
headphones.
J400 also contains a switch for the 16V supply that appears at the rear single phono socket. When a suitable plug is inserted into
the headphone socket the connection between pins 8 and 9 of J400 is broken removing the 16V from pin 8. This is sensed by pin 19
of I001 (the micro processor) via the potential divider R473 and R474, this tells I001 to change the audio menu's to the headphone
versions (Dolby models only).
The 16V is also removed from the rear phono socket, this turns off the infra red surround sound speaker transmitter or the power
console (if connected - not supplied with all models).
For non Dolby models the speaker leads are connected directly to P400. For Dolby models the internal speakers are connected
from P400 via a sub panel screwed to the rear of the chassis frame. This houses two din type speaker sockets with internal
switches. The switches disconnect the internal left and right speakers when a plug is inserted, thus allowing external left and right
speakers to be fitted.
DOLBY DECODER.
The Dolby decoding is provided by IF01 (YSS241) The signals which are sent to this device from I400 in the I2S format, and are:-
SD0 (Pin Of I400) - the Left and Right channel data (before Dolby decoding)
SCK (Pin Of I400) - the system or bit clock
WS (Pin Of I400) - the word select line, provides selection between the Left and Right samples on the SDO Line.
IFO1 is provided with an 18.432 MHz clock via pin 1 of I400 (SYSCLK),a reset line from pin 4, and is I2C controlled. The Pro-logic
signals that the device decodes are provided in I2S form at pins 40 and 41 (DACS1 and DALR) These signals are in a 32bit per
channel format ( The MSP4310D uses 16 bit) and must therefore pass through a conversion IC IF02. This IC also takes a Bit clock,
DABC from pin 36 of IF01. IF02 then provides the 16 bit pro-logic I2S channels as SDI1 and SDI2 on pins 14 and 20 of I400.
I400 then passes these signals through DAC's so that the Left, Right, Centre and Surround signals appear at pins 29, 28,26 and 25
as Pre-L, Pre-R, Pre-C and Pre-S respectively. Theses are then amplified by 3dB by op-amp IF03 to become AmpL, AmpR, Centre
and Surround. These then pass through a buffer and filter network to the four way phono plug JF01. The AmpL and AmpR signals
split off before the buffers to the amplifier I401 via dividing resistors R443/R439 and R446/R447 and are decoupled by C443 and
C445. The operation of the amplifier is explained elsewhere in this manual.
DEFLECTION
100HZ HORIZONTAL DEFLECTION STAGE (A8)
The 2H output from UQ01 (the feature box) from pin 30 is fed via K66 and RH03 to pin 24 of IE02 TDA9330 the "HOP".
The horizontal drive is then output from pin 8 is passed through an emitter follower stage (Q705) to the gate of Q701B. A mosfet is
used to sharpen the switching edges and reduce the temperature of the power transistor Q751. The drain of Q701B is fed from the
+B via R701 and the primary of the drive transformer T702. The secondary of the transformer drives the base of the power transistor
Q751, the collector of which is supplied from the +B via R751, L700 and the primary of the FBT T701. The emitter is connected to
ground via R760 a 1 Ohm 10W resistor ( R760 should be kept away from Q751 heatsink to reduce heat transfer) which is a sense
resistor for the protection circuit.
The capacitive divider network C717 and C708 produce a line pulse which is sampled by Z704 and clamped by D713 and D714 this
is then returned to pin 13 of IE02.
50HZ HORIZONTAL DEFLECTION STAGE (D8)
The HA OUT from pin 60 of I200 TDA9320 the "HIP" is fed via K66 and RH03 to pin 24 of IE02 TDA9330 the "HOP".
The horizontal drive is then output from pin 8 is fed to the base of Q701. The collector of Q701 is supplied from the +B via R701 and
the primary of the drive transformer T702. The secondary of T702 drives the base of the power transistor Q751. The collector of
Q751 is supplied from the +B via R751, L700 and the primary of the FBT T701. The emitter is connected to ground via R760 which
is a sense resistor for the protection circuit.
The capacitive divider network C717 and C708 produce a line pulse which is sampled by Z704 and clamped by D713 and D714 this
is then returned to pin 13 of IE02.
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