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Delay-trigger
This trigger acquisition is used in applications if you want to delay the data
collecting process after a specified trigger event. The delay time is controlled by
the value, which is pre-loaded in the Delay_counter (32-bit). The clock source is
the Timebase clock. When the count reaches zero, the counter stops and the
board start to acquire data. When the internal 48 MHz is set as Timebase clock,
the delay time is in the range of 20.8 ns to 89.47 s. If the Timebase clock is from
external clock (48 MHz to 1 MHz), the delay time can be varied by user's setting.
Figure 3-10
Digital trigger
There are positive and negative conditions in digital trigger. It is used when a rising
or falling edge is detected on the digital signal. Positive condition is used when it
triggers from low to high, while high to low when the negative condition is used.
Figure 3-11
Keysight U2300A Series User's Guide
Delay-trigger
Positive and negative edge of digital trigger.
Features and Functions
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