JVC UX-H33 Manuel D'instructions page 34

UX-H33
4.11 LC72723(IC3): RDS demodulation
• Pin layout
VREF
1
MPXIN
2
Vdda
3
Vssa
4
FLOUT
5
CIN
6
TES
7
XOUT 8
• Block Diagram
• Pin functions
Pin No. Symbol
1 VREF
2 MPXIN
3 Vdda
4 Vssa
5 FLOUT
6 CIN
7 TEST
8 XOUT
9 XIN
10 Vssd
11 Vddd
12 MODE
13 RST
14 RDDA
15 RDCL
16 RDS-ID/READY
1-34 (No.22044)
RDS-ID/READY
16
RDCL
15
RDDA
14
RST
13
MODE
12
Vddd
11
10 Vssd
9 XIN
VREF FLOUT
+5V
Vdda
REFERENCE
VOLTAGE
Vssa
57kHz
BPF
MPXIN
(SCF)
ANTI ALIASING
FILTER
CLK(4.332MHz)
TEST
TEST
XIN
I/O
O Reference voltage output (Vdda/2)
I Baseband (multiplexed) signal input
- Analog power supply (+5V)
- Analog ground
O Subcarrier input (filter output)
I Subcarrier input (comparator input)
I Test input
O Crystal oscillator output (4.332MHz)
I Crystal oscillator input (exeternal reference input)
- Digtal ground
- Digtal power supply
I Read mode setting (0:master, 1:slave)
I RDS-ID/RAM reset (positive polarity)
O RDS data output
I/O RDS clock output (master mode)/RDS clock input (slave mode)
O RDS-ID/READY output (negative polarity)
CIN
+
RECOVERY
PLL
(1187.5Hz)
(57kHz)
-
VREF
SMOOTHING
FILTER DECODER
(128-bits)
DETECT
OSC
XOUT
Function
+5V
CLOCK
Vddd
Vssd
DATA
RDDA
RDCL
RAM
MODE
RST
RDS-ID
RDS-ID/
READY