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MS-7053 ATX Mainboard
Advanced Chipset Features
DRAM Timing Selectable
Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect) EEPROM
on the DRAM module. Setting to [Auto By SPD] enables DRAM timings and the follow-
ing related items to be determined by BIOS based on the configurations on the SPD.
Selecting [Manual] lets users configure the DRAM timings and the following related
items manually. Setting options: [Manual], [Auto By SPD], [Turbo], [Ultra].
CAS Latency Time
This controls the CAS latency, which determines the timing delay (in clock cycles)
before SDRAM starts a read command after receiving it. Settings: [Auto], [2], [2.5],
[3]. [2] increases the system performance the most while [3] provides the most stable
performance.
DRAM RAS# to CAS# Delay
When DRAM is refreshed, both rows and columns are addressed separately. This
setup item allows you to determine the timing of the transition from RAS (row address
strobe) to CAS (column address strobe). The less the clock cycles, the faster the
DRAM performance. Setting options: [Auto], [2], [3], [4], [5].
DRAM RAS# Precharge
This item controls the number of cycles for Row Address Strobe (RAS) to be allowed
to precharge. If insufficient time is allowed for the RAS to accumulate its charge
before DRAM refresh, refresh may be incomplete and DRAM may fail to retain data.
This item applies only when synchronous DRAM is installed in the system. Setting
options: [Auto], [2], [3], [4], [5].
Precharge delay (tRAS)
This setting determines the precharge delay, which determines the timing delay for
DRAM precharge. Setting options: [Auto], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13],
[14], [15].
E-3-6
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