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INTEGRATED CIRCUITS BLOCK DIAGRAM
PortC
PortB
PortA
(7:0)
(7:0)
(7:0)
GPIO
PWM
VYUV
(7:0)
YUV
to
R G B
YPbPr
Processing
to
R G B
GRGB
(23:0)
GVS
GHS
GCLK
Sync
Auto Image
Decoder
Decoder
Optimisation
VVS
And Timer
VHS
VCLK
GREF GFBK
Premary
Video Port
ITU-R BT 601
Secondary
Video
Video Port
Unit
ITU-R BT 6656
Digital
Graphic Port
24-Bit
Two-Wire
Interface
PW1230
Interna Block Diagram
LCD03B
First issue 04 / 04
JTAG Debugger
IR
2-Wire
16-Bit
Decoder
Serial
Microprocessor
Processor
Memory
Interface
Memory
Buffer
Graphic
or Video
Port Pixel
Reset
Power On
Reset
Reset
Memory Unit
Input Unit
Film-Mode
Motion
Previous
Detection
Video
&
Noise
I-Channel
Reduction
P-Channel
Down
Scaler
Proramming Unit
A
D
CS
(19:1)
(15:0)
(1:0)
Processor ROM
Wtchdog
RAM Interface
Timers
On-
Screen
Display
OSD
Color
Scaler
and
Matrix
Gain
MCLK DCLK
UCLK
PLL
PW113 Image Processor
and
Internal Block Diagram
Oscillator
X1
X0
Display Unit
Detection
(3:2&2:2)
I-Channel
Deinterlacer
Premary
Picture
(l/P)
P-Channel
R G B
Enhancement
Color
Lut
Screen
63
NMI
TxD
RxD
Interrupt
UART
Controller
Microprocessor BUS
Color
Color
LooKup
Space
Tables
Expander
Display
Timing
Generator
Display
Timing
Up
Scaler
Video
Y U V
CSC
VSync/
Blue
HSync
DACs
Timing
DRGB
(23:0)
DRGB
(23:0)
DVS,DHS
DEN,DCLK
Digital
Output
Timing
Analog
Output
Digital
Output
Data
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