QRP Labs QCX-mini CW Mode D'emploi page 116

damage to the ATmega328P processor or maybe prevent damage altogether. Perhaps.
(don't feel tempted to try it intentionally).
Audio ADC
There are two audio connections from the receiver signal chain to the microcontroller. One
is connected at the output of the I-Q balance adjustment potentiometer. In other words, the
input to the CW filter. The second audio connection is connected after the final audio
amplification gain stage. Both of these audio signal channels are fed to Analogue to Digital
Converter (ADC) inputs of the microcontroller.
The circuit diagram (right) shows the circuit at AUDIO 1 (ADC channel 0) which is
connected to the audio amplifier output. The purpose of the circuit is to remove the DC bias
from the audio signal, and apply a new bias of 2.5V, to bias it to the middle of the ADC's
input range. The 1K resistor in series with the ADC pin is intended to provide some kind of
limited protection to the microcontroller in the event that the voltage falls outside the range
0-5V. A simpler circuit is used on the AUDIO 2 channel as the DC bias is already 2.5V so
the signal is within the range 0-5V.
The ADCs in the ATmega328P have 10-bit resolution which translates to about 5mV. The
ADC conversion result is a number in the range 0-1023, with 512 representing zero. An
audio voltage of +/- 2.5V can therefore be measured. In practice, the audio signal is much
less than this, which means the full ADC range is not really used. The AUDIO2 channel
(connected at the CW filter input) has even less amplitude so is not used for anything
except the BPF Alignment procedure, which has a very strong signal.
Frequency Counter
The frequency counter test pin input is connected directly to the microcontroller's 16-bit
Timer1 input pin.
There is a 1K series resistor (R55) to connect it also to the
Si5351A's Clk2 output. This is used during the optional
GPS-disciplined 27MHz reference crystal frequency
measurement. In this function, the Si5351A is configured to
route its raw 27MHz output, divided by 4, to its Clk2 output.
This passes through the 1K resistor R55, to the
microcontroller. The 1K resistor provides protection to the
Si5351A in the event you accidentally have something
connected to the FREQ input pin, and the Si5351A is
operating its Clk2 output at the same time.
Since the 3.3V peak-peak signal from the Si5351A is rather
marginal for operating the Timer1 input, a 3.9K pullup
resistor increases its center point. Now "low" is 1.02V and "high" is 3.65V, which is enough
to trigger the Timer1 input reliably.
The frequency counter can operate from 0 to 8MHz theoretically, assuming a clean 50%
duty-cycle squarewave signal of sufficient amplitude. The 8MHz upper bound is a limitation
of the AVR processor which has a synchronous timer input, and can only count to 40% of
the system clock frequency (40% of 20MHz is 8MHz).
The signal to be counted must satisfy the logic thresholds of the ATmega328P, namely a
"low" or "0" is less than 1.5V, and a "high" or "1" is greater than 3.5V.
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QCX-mini assembly Rev 1.05_Fr