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GENERAL BLOCK DIAGRAM - SYNOPTIQUE GÉNÉRAL - BLOCKSCHALTBILD ALLGEMEIN - SCHEMA A BLOCCHI GENERALE - ESQUEMA DE BLOQUES GENERAL
+5V
GND
IC2_DATA_FP
16x9_FORMAT
UC_IRQ
IR
KDB 2
KDB 1
ID100
driver
out1
out2
drawer
motor
S_START
S_D_VALID
S_DATA
Pick-up
S_B_CLK
SRVO IRQ
I2C_DATA
I2C_CLK
SOFT_RST
JTAG Port
SYS_RESET
+3.3V
YE216
27Mhz
crystal
IE216
pi03.1
IG100_P7
pi02.4
pi03.6
in1
slide_in
in2
slide_out
current
vcc2
detector
slide_oc
TD100
TD101
b_sync
b_flag
b_data
b_bclk
irq(0)
sdata
sclk
dxx_rst
IG501
In
Out
rst
cd0 –dd15
dd0 – dd15
ba0 – ba11
ba0 –ba11
ldqm
ldqml
we
sdwe
SDRAM
cas
sdcas
1Mx16
ras
sdras
IG102
clk
memclk
IG103
udqm
dqmu
cs
sdcs(-)
118
pixclk
5 sda
Sdata
EEPROM
8Kx8
6 scl
Sclk
Cv_out
Y_out
C_out
R_out
G_out
B_out
md0-md15
maddr1 -21
md0 – md15
maddr1 - 21
we
MASK ROM
oe
1M x 16
ce3
ce0
PCM_OUT
µP
SCLK
LRCLK
IG100
PCM_CLK
SPDIF_OUT
md0 – md7
maddr1 - 16
we0
we
FLASH
oe
1M x 16
we1
a0
IH105
ce
oe
motw
ras0
cas0
cas1
epf_irq
UY500
FILTER
FILTER
UY500
FILTER
FILTER
UY500
FILTER
FILTER
UY505
FILTER
FILTER
UY505
FILTER
FILTER
UY505
FILTER
FILTER
+5V
-5V
CINCH
DACONVERTER
UA501
SDATA
L/OUT
FILTER
LEFT
SCLK
UA501
RIGHT
LRCLK
R/OUT
FILTER
MCLK
CONNECTOR
UA500
LEFT
FILTER
UA500
RIGHT
FILTER
OPTICAL LINK
AV Interface BOARD
md0 – md15
maddr1 - 12
oe
DRAM
w
2Mx16
+8V
+12V
IP302
ras
8V regulator
IM121
cas
+3.3V
+5V
IP303
3.3V regulator
cas
Switch mode
power supply
-5V
EPF_IRQ
Main BOARD
Power Supply BOARD
CINCH
SVHS
Conn.
CONNECTOR
To TV part
AC
mains
180 -
264 vac
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Table des Matières
