TTl input:
Trig-level LOW ............................................ ≤ 0.8 VDC
Trig-level HIGH ................................................ ≥ 2.0 VDC
Input impedance ........................................ ≥ 100 kΩ
s0 input acc. to DIN 43 864:
Trig-level LOW ............................................ ≤ 2.2 mA
Trig-level HIGH ............................................... ≥ 9.0 mA
Input impedance ........................................ 800 Ω
Analogue output:
Current output:
Signal range ............................................... 0...20 mA
Min. signal range ........................................ 5 mA
Max. offset.................................................. 50% of selected max. value
Updating time ............................................. 20 ms
Load (max.) ................................................. 20 mA / 600 Ω / 12 VDC
Load stability .............................................. < ± 0.01% of span / 100 Ω
Current limit ................................................ ≤ 23 mA
Voltage output through internal shunt:
Signal range ............................................... 0...10 VDC
Min. signal span ......................................... 250 mV
Max. offset.................................................. 50% of selected max. value
Load (min.) .................................................. 500 kΩ
Active outputs (NPN / PNP):
I max. source ............................................... 10 mA
I max. sink ................................................... 130 mA
V max. ......................................................... 28 VDC
f/f converter output:
Signal range ............................................... 0...1000 Hz
Min. pulse width ......................................... 500 µs
Max. pulse width ........................................ 999 ms
Max. duty cycle .......................................... 50%
Frequency generator:
Min. period ................................................ 50 µs
Max. frequency ........................................... 20 kHz
Duty cycle ................................................... 50%
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