▶
OC Step
Ths tem s used to set how many steps for base colck overclockng.
▶
OC Step Count Tmer
Ths tem s used to set the buffer tme for every step.
▶
Adjust CPU Rato
Ths tem allows you to adjust the CPU rato. Settng to [Startup] enables the CPU
runnng at the fastest speed whch s detected by system.
▶
Adjusted CPU Frequency (MHz)
It shows the adjusted CPU frequency (Base clock x Rato). Read-only.
▶
OC Gene
Ths tem s used to enable/ dsable the OC Gene functon.
▶
Memory-Z
Press <Enter> to enter the sub-menu.
▶
DIMM1~4 Memory SPD Informaton
Press <Enter> to enter the sub-menu. The sub-menu dsplays the nformatons of
nstalled memory.
▶
Current DRAM Channel1~4 Tmng
It shows the nstalled DRAM Tmng. Read-only.
▶
DRAM Tmng Mode
Select whether DRAM tmng s controlled by the SPD (Seral Presence Detect)
EEPROM on the DRAM module. Settng to [Auto] enables DRAM tmngs and the
followng "Advance DRAM Configuraton" sub-menu to be determned by BIOS based
on the configuratons on the SPD. Selectng [Manual] allows users to configure the
DRAM tmngs and the followng related "Advance DRAM Configuraton" sub-menu
manually.
▶
Advance DRAM Configuraton
When the DRAM Tmng Mode s set to [Manual], ths submenu wll avalabled. Press
<Enter> to enter the sub-menu.
▶
CH1/ CH2 1T/2T Memory Tmng
Ths tem controls the SDRAM command rate. Select [1N] makes SDRAM sgnal
controller to run at 1N (N=clock cycles) rate. Selectng [2N] makes SDRAM sgnal
controller run at 2N rate.
▶
CH1/ CH2 CAS Latency (CL)
Ths controls the CAS latency, whch determnes the tmng delay (n clock cycles)
before SDRAM starts a read command after recevng t.
Englsh
En-39