Publicité
CARTRIDGE CONNECTORS
2.
Pin
Pin
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
a1
43
45
47
49
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17-32
28
49
50
vo
Name
cs
o
0
cs12
Reserve
=
WAIT
1
o
M1
0
IORQ
WR
o
0
RESET
o
A9
o
A11
o
A7
o
A12
o
A14
o
A1
o
A3
o
A5
vo
Dt
vo
D3
vo
D5
vo
D7
GND
=
GND
=
-
+5V
-
+5V
SOUNDIN
1
Name
Content
cs1
ROM
cs2
ROM
cs12
ROM
SLTSL
Slot
Reserve
Reserved
RFSH
Refresh cycle signal
CPU's
WAIT
INT
Interrupt
Mi
Signal expressing
This signal controls direction
BUSDIR
Cartridges are selected and
cartridge at data transmission time
SE
IORG
request
VO
MERG
Memory
WR
Write
RD
Read
RESET
System reset signal
Reserve
Reserved
Address
A15
AO
—
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
addresses
4000
7FFF
-
addresses
8000
BFFF select
—
addresses
4000
-BFFF
select signal
line
use inhibited
signal
—
WAIT
request signal
request
signal to
fetch cycle
CPU
signal
request signal
timing signal
timing
signal
use
line
signal
—
bus
signals
1
2
Name
€82
SLTSL
RFSH
INT
BUSDIR
MERQ
RD
Reserve
A15
A10
A6
A8
A13
AO
A2
A4
DO
D2
D4
D6
CLOCK
Swi
sw2
+12V
—12V
select
signal
signal
select
signal
(for 256k
CPU
external data bus buffer
of
level is
output
from
L
inhibited
vo
o
o
o
ï
1
°
0
o
o
o
o
[e]
o
0
o
vo
vo
vo
vo
o
=
==
-
-
ROM)
each
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